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Altera_Forum's avatar
Altera_Forum
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10 years ago

Functional simulation on a module by module basis

I am an established FPGA engineer, having many years of experience with Xilinx ISE and Vivado. I have just started using Quartus II 9.1 SP2 in my new job, an old version is used for various reasons.

For the life of me, I cannot figure out how to perform a behavioral/functional simulation on an individual module (schematic or VHDL) rather than the top level entity. None of the tutorials I have found cover this, is there something silly I am missing here?

Trying to find the child modules pins in the vector waveform editors node finder just results in no matches being found.

5 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    10 years ago

    The Quartus simulator is rather basic - you would be much better off doing your module simulations in modelsim. Quartus can only simulate a post sysnthesis netlist. With an HDL testbench it would simulate much faster and you would have far more control.

    If you have to use the quartus simulator for some reason, you will have the change the top level design in the project:

    Assignments -> settings -> top level endtity - > select the unit you want to test.

    I assume you are using such an old version of quartus (6 years old) for the very old device support?
  • Altera_Forum's avatar
    Altera_Forum
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    10 years ago

    I usually just write a test bench for the module of interest and compile and simulate that. (Just calling the required files).

    I never use quartus for simulation. I'm always using ModelSim, Riviera, or VCS independently however.

    Pete
  • Altera_Forum's avatar
    Altera_Forum
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    10 years ago

    Many thanks Tricky, I am having to use 9.1 for now due to old device support and it is what is installed and licensed, but that will be changing soon. Thanks for clarifying on what 9.1's capabilities are.

    @Anakha: I usually write VHDL testbenches for each module :). Many thanks!
  • Altera_Forum's avatar
    Altera_Forum
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    10 years ago

    Many thanks Tricky and Ankha - I usually write VHDL test benches. We are using 9.1 because it is installed, licensed and ready to go. The latest version should be installed shortly mind.

  • Altera_Forum's avatar
    Altera_Forum
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    10 years ago

    If you're writing VHDL testbenches, then you can go directly to modelsim without using quartus at all (other than to convert the schematic files).