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Altera_Forum
Honored Contributor
8 years agoin VHDL - its simple, especially if you use the fixed point package:
use ieee.fixed_pkg.all;
....
signal a : sfixed(7 downto -8); -- 1 sign bit, 7 integer bits, 8 fraction bits - ie. integer offset by 2^8
signal b : sfixed(15 downto -16);
...
b <= a*a;
this can all be done with the numeric_std package, but you need to keep track of the offset yourself.