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Altera_Forum
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8 years ago

FSM miley machine

I'm new to Verilog. I was trying to write the next Finite State Machines (miley machine) in Verilog: https://i.stack.imgur.com/9rvCj.jpg One of the attached file (called FSM.v) is the pr...
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Altera_Forum
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8 years ago

You can also use the State Machine Editor that comes packaged with the Altera Quartus tool to draw your FSMs and have it generate the VHDL/Verilog code for you.

File -> New -> State Machine File.

Here you can specify the inputs, outputs, states and transitions. Once done, select the language you want to generate (VHDL/Verilog) and click Generate. This will add the FSM and generated code to your project.