FSM miley machine

For the SM you've put up, here's the Verilog Code..Since the outputs are on the States and not on the transitions, the state machine code will be like below.

module SM1 (
                  clock,
                  reset,
                  in1,
                  out1
                 );
    input clock;
    input reset;
    input in1;
    output out1;
    reg out1;
    reg  current_state;
    reg  next_state;
    parameter S0=0,S1=1,S2=2;
    always @(posedge clock or negedge reset)
    begin
        if (~reset) begin
            current_state <= S0;
        end
        else begin
            current_state <= next_state;
        end
    end
    always @(current_state or in1)
    begin
        out1 <= 1'b0;
        case (current_state)
            S0: begin
                if ((in1 == 1'b1))
                    next_state <= S1;
                else if ((in1 == 1'b0))
                    next_state <= S0;
                else
                    next_state <= S0;
                out1 <= 1'b0;
            end
            S1: begin
                if ((in1 == 1'b0))
                    next_state <= S2;
                else if ((in1 == 1'b1))
                    next_state <= S0;
                else
                    next_state <= S1;
                out1 <= in1;
            end
            S2: begin
                if ((in1 == 1'b0))
                    next_state <= S1;
                else if ((in1 == 1'b1))
                    next_state <= S2;
                else
                    next_state <= S2;
                out1 <= 1'b1;
            end
            default: begin
                out1 <= 1'b0;
            end
        endcase
    end
endmodule // SM1