Forum Discussion
Altera_Forum
Honored Contributor
8 years agoFSM miley machine
I'm new to Verilog. I was trying to write the next Finite State Machines (miley machine) in Verilog: https://i.stack.imgur.com/9rvCj.jpg One of the attached file (called FSM.v) is the pr...
Altera_Forum
Honored Contributor
8 years agoForgive me but the code you've posted, Anand, is still fundamentally wrong - in the same way the original code was. You cannot assign 'out' a value in two different always blocks, which you are still doing.
There a several other aspects of the code you've posted that I also dislike - both 'next_state' and 'present_state' being update in the same always block, both assigned with non-blocking assignments. 'present_state' isn't going to update for two clock cycles. So, there's also a very good change 'out' takes the wrong value for the extra, unnecessary, clock cycle. Verilogoz, I much prefer the code you originally posted - save the minor mistake it had. I suggest you work with that as a basis for your solution. Cheers, Alex