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Honored ContributorFSM miley machine
I'm new to Verilog. I was trying to write the next Finite State Machines (miley machine) in Verilog: https://i.stack.imgur.com/9rvCj.jpg One of the attached file (called FSM.v) is the pr...
Altera_ForumHonored Contributor
Honored ContributorHi Verilogoz,
1.Did you Simulate?There is a mapping error in FSM_tester. 2.Clock should be given at right bock.(Sequential block not at combination block). 3.Mealy state machine output change when ever there is change in input or state. FSM.v
module FSM (clock,reset,in,out);
input clock,reset,in;
output out;
wire clock,reset,in;
reg out;
reg present_state;
reg next_state;
localparam A=2'b00, B=2'b01, C=2'b10;
always @(posedge clock )
begin
case (present_state)
A: if(in) begin next_state <= B; end
else begin next_state <= A; end
B: if(in) begin next_state <= A; end
else begin next_state <= C; end
C: if(in) begin next_state <= C; end
else begin next_state <= B; end
endcase
end
always @(present_state or in or posedge reset)
begin
if(reset)
begin
present_state = 2'b00;
out = 1'b0;
end
else
begin
present_state=next_state;
case (present_state)
A:
out = 1'b0;
B:
out = in;
C:
out = 1'b1;
endcase
end
end
endmodule
module FSM_tester;
reg clock, reset, in;
wire out;
FSM U0 (
.clock (clock),
.reset (reset),
.in (in),
.out (out)
);
initial begin
clock = 1;
reset = 1;
in = 1;
$display("Simulation...");
# 2;
if (out !== 1'b0) $display("Failed1"); // Check reset
reset = 0;
# 2;
if (out !== 1'b0) $display("Failed2");
# 2;
if (out !== 1'b1) $display("Failed3");
# 2;
if (out !== 1'b0) $display("Failed4");
# 2;
if (out !== 1'b1) $display("Failed5");
# 2;
if (out !== 1'b0) $display("Failed6");
$display("Done...");
end
always begin
# 1 clock = !clock;
end
always begin# 3 in=~in;
end
endmodule
