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Altera_Forum
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9 years ago

FSK Modulation in VHDL

Hello, I have written a testbench which performs FSK modulation. The testbench should perform the auto checks such that when fsk_data_i(0) = '1' then I need to push fsk_u_i to fsk_mod_o whereas...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
9 years ago

I tried with the wait statement and its working well, but actually I need another method where within the module I can change the input values once all the bits of fsk_data_i are checked. Please help me to solve this issue. Thanks in advance