FSK Modulation in VHDL

have a look at my changes (not tested), counters as integers (0 to 1023 & 0 to 21)

begin
  process(resetn, clk)
  begin
    if resetn = '0' then
      fsk_mod_o <= (others => '0');
      cnt_s     <= 0;
      cntdiv_s  <= 0;
    elsif clk'event and clk = '1' then
      if enable = '1' then
          cntdiv_s <= cntdiv_s + 1;       
          if cntdiv_s = 1023 then  
              cntdiv_s <= 0;    
              cnt_s <= cnt_s + 1; 
              if cnt_s = 21 then
                 cnt_s <= 0;
              end if; 
         end if;
     
           if fsk_data_i(cnt_s) = '1' then  
              fsk_mod_o <= std_logic_vector(fsk_u_i);                
           else
              fsk_mod_o <= std_logic_vector(fsk_l_i);
           end if;
     
         end if;
       end if;
    end if;
  end process;