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Altera_Forum
Honored Contributor
Honored ContributorFSK Modulation in VHDL
Hello, I have written a testbench which performs FSK modulation. The testbench should perform the auto checks such that when fsk_data_i(0) = '1' then I need to push fsk_u_i to fsk_mod_o whereas...
Altera_ForumHonored Contributor
Honored ContributorI just don't know why still I get the error " Index 22 out of bound 21 downto 0". Please help me out to solve this issue.
