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Altera_Forum
Honored Contributor
Honored ContributorFSK Modulation in VHDL
Hello, I have written a testbench which performs FSK modulation. The testbench should perform the auto checks such that when fsk_data_i(0) = '1' then I need to push fsk_u_i to fsk_mod_o whereas...
Altera_ForumHonored Contributor
Honored ContributorYour problem is difficult to read due to too much type conversion and lack of concept explanation and lack of full code
The issue of bit out of range should be obvious. your data is 22 bits yet the counter is exceeding 21 index. you need to account for that and constrain your counter.
