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Altera_Forum
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10 years ago

FSK Modulation in VHDL

Hello, I have written a testbench which performs FSK modulation. The testbench should perform the auto checks such that when fsk_data_i(0) = '1' then I need to push fsk_u_i to fsk_mod_o whereas...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

if (fsk_data_i(to_integer((unsigned(cnt_s)))) = '1')

'1' is std_logic, how come it passed compilation

sorry my fault(it is index)