New Contributor
Frequent ContributorHi ,
Please let us know any timing violation or other warning messages appeared after connecting the extra ports and Compiling / generating in Quartus.
Thanks and Regards
Anil
New ContributorI have attached the generation warning and system messages for board.qsys and kernel_system.qsys after adding the new components.
After adding the components, I compiled the Quartus project to debug any errors in my design. The compilation went successfully. The warnings are attached in the compilation_warning.txt file.
Note: The error I mentioned in my post occurs in the fitter stage. I have tried another design by creating a bridge between kernel and flash memory. I faced the exact same error.
Any help or pointer to solve the problem will be highly appreciated.
ModeratorThank you for your patients, after some investigation on the warning as well as errors, we would suggest and try to look at the top level verilog files (i.e. top.v) and compare it with the connection between the freeze wrapper and board.qsys to see if any anomaly for connection is found.
Another perspective that we can try out is maybe better to try and build a flat flow to see if the design can be synthesized and check the RTL viewer for the connection. (most likely you will see some floating ports).
Warm regards.
ModeratorBy any chances did you managed to look into the suggest above to see if it works?
Warm regards.
BB
