ContributionsMost RecentMost LikesSolutionsRe: Freeze wrapper error in Arria 10 Custom Platform Customization example I have attached the generation warning and system messages for board.qsys and kernel_system.qsys after adding the new components. After adding the components, I compiled the Quartus project to debug any errors in my design. The compilation went successfully. The warnings are attached in the compilation_warning.txt file. Note: The error I mentioned in my post occurs in the fitter stage. I have tried another design by creating a bridge between kernel and flash memory. I faced the exact same error. Any help or pointer to solve the problem will be highly appreciated. Freeze wrapper error in Arria 10 Custom Platform Customization example Hi, I was trying the Intel Arria 10 Custom Platform Customization Example from Compiling and Customizing an Intel® Arria® 10 Custom Platform for OpenCL* user guide (2018.10.30). I am using Quartus prime pro 17.1.2 version. After copying the files to the original custom platform directory, I was compiling my vector_add kernel to regenerate the new custom platform. I'm getting the following errors: Error (18514): Child partition "freeze_wrapper_inst|kernel_system_inst" expects its parent to drive input port "kernel_sc_fifo_in_valid", but this port is not driven from its parent partition "|". Modify either the child or parent partitions so that all expected signals are correctly driven from the parent partition. Error (18624): Partition "freeze_wrapper_inst|kernel_system_inst" contains output port "kernel_sc_fifo_out_valid" that is ignored by its parent partition "|". Consider modifying your design so that all output ports are connected to their parent partitions. I am getting these two sets of errors on all the following ports that I added to the freeze wrapper. input [63:0] board_kernel_sc_fifo_in_data, input board_kernel_sc_fifo_in_valid, output board_kernel_sc_fifo_in_ready, output [63:0] board_kernel_sc_fifo_out_data, output board_kernel_sc_fifo_out_valid, input board_kernel_sc_fifo_out_ready While instantiating the kernel_system in freeze_wrapper, I have connected these ports to the corresponding ports of kernel_system. Therefore, kernel_system is actually being driven by its parent freeze_wrapper. Any help with debugging the issue will be highly appreciated. I have attached my log file here. Re: Modifying the a10_ref OpenCL BSP Error Can you please mention how you resolved the issue? I am having the exact same error.