Free Tools?

Well done guys, keep up the good work.

Although, being realistic, it will take A LOT to disrupt this market. Until it gets mainstream company support, things like this are constanly in danger of dying through lack of support and updates. Open source often is only really open to those technically able, or have the time to investigate. Companies cannot usually afford the man hours to use something like this.

Big companies are using VHDL 2008, System Verilog 2012, UVM (as well as other open source libraries like OSVVM, UVVM), then there are all the tools promoting the virtues of Python for Verification and HDL generation. It feels rather fractured.

These open source tools are A LONG way from gaining mainstream adoption.