Free Tools?

@Tricky,

I don't get over to these forums much, perhaps I should more often. That said, I am working within an open source FPGA community that you might wish to be aware of.

• Most of my work revolves around yosys (http://www.clifford.at/yosys/). yosys (http://www.clifford.at/yosys/) is a free/open source synthesizer. It does have preliminary support for Altera parts, just ... not yet enough to build my own projects (https://github.com/zipcpu/arrowzip/). It currently does quite well with iCE40 designs, and I expect it will handle Xilinx 7-series designs soon enough. There's just no one working on the Intel back end right now. (Hear that, Intel? We'd love to have you help out, rather than to have Xilinx be the first major FPGA chipset we support ... there's still time!)

• yosys (http://www.clifford.at/yosys/) can produce outputs in many formats, including a variety of ASIC formats as well.

• yosys (http://www.clifford.at/yosys/) can also output your design in a number of formats necessary to formally verify the design using a variety of free formal solvers. This is how I have been using it recently: as a front end for formal verification (http://zipcpu.com/blog/2017/10/19/formal-intro.html). Checkout symbiyosys (https://symbiyosys.readthedocs.io/en/latest/) if you are interested, or even this article (http://zipcpu.com/blog/2018/03/10/induction-exercise.html) for an example of how to use it.

• I have done all of my simulation work using verilator (http://zipcpu.com/blog/2017/06/21/looking-at-verilator.html). verilator (http://zipcpu.com/blog/2017/06/21/looking-at-verilator.html) is another free and open source tool, this time one that converts Verilog (or system verilog) to C++. I've then used that C++ quite successfully to drive co-simulations of my design(s) with hardware simulators (http://zipcpu.com/blog/2017/06/23/my-dbg-philosophy.html) for all of the hardware on the boards I am working with: flash, SDRAM, uarts (https://github.om/zipcpu/wbuart32), and even vga simulation (https://github.com/zipcpu/vgasim/)

• I've also been working on slowly building up a library of free and open source ip components (https://github.com/zipcpu). You can find it on my github page. (https://github.com/zipcpu) Some highlights include ...

• The zipcpu (https://github.com/zipcpu/zipcpu) is a free and open source CPU that can be used in place of many other proprietary CPU's out there. You do get what you pay for, though ... while I have full gcc+newlib (https://github.com/zipcpu/zipcpu/tree/master/sw) support for the zipcpu (https://github.com/zipcpu/zipcpu), I don't yet have gdb support and the zipdbg debugger is not a source level debugger. Linux support has been a goal for years, but although the hardware is just about there the software is far from ready.

• I've put together a series of posts on dsp filtering (http://zipcpu.com/dsp/dsp.html), describing not only several different filters (https://github.com/zipcpu/dspfilters/) but also how you might test them (http://zipcpu.com/dsp/2017/12/06/fastfir-tb.html). Many of these are built for high speed, high bandwidth applications, but I did spend some time discussing how to build a slower filter (http://zipcpu.com/dsp/2017/12/30/slowfil.html) as well.

• There's also a discussion of several methods of generating sine/cosine waves (https://github.com/zipcpu/cordic/) on the blog as well--to include a description of how to build and test (http://zipcpu.com/dsp/2017/10/02/cordic-tb.html) a cordic (http://zipcpu.com/dsp/2017/08/30/cordic.html) of arbitrary size. A waiting article will discuss how to generate a better quality sine wave with only two multiplies.

• There's a discussion of how to build a numerically controlled oscillator (http://zipcpu.com/dsp/2017/12/09/nco.html), or even a digital phase lock loop (http://zipcpu.com/dsp/2017/12/14/logic-pll.html)

• I also try to be responsive to my patreon supporters (https://www.patreon.com/zipcpu) (there aren't that many of them yet), so if these are topics you are interested in then please feel free to support my work (https://www.patreon.com/zipcpu). Every donation goes a long ways, even the smallest ones

• My focus has always been how to get the most out of your fpga (http://zipcpu.com/blog/2017/06/12/minimizing-luts.html) $'s, since I'm sure you (like me) want bleeding fast performance without paying the pocket book costs required to get it. This also places a different focus on open source IP when compared with the proprietary IP: open source IP is focused on getting the most capability from the board you've already paid for, proprietary vendor supplied IP has no such limitations. Indeed, it's no skin off Intel or Xilinx's back if their IP is too big to fit on your chip, they'd rather you bought the most expensive chip anyway.

Of course, I'm not a community, and I mentioned that a community existed. Please feel free to join myself and others on Freenode's IRC, and you may meet some of the individuals involved. I tend to inhabit the# #fpga channel, the# #verilog channel, and even the# yosys channel under the screen name of ZipCPU. We'd love to hear from you, just please ... stick around. Time zones being what they are can mean that it takes 24-hrs or so to get a response to any request on the channel. You can also look me up on twitter (https://twitter.com/zipcpu) and browse my subscribers--that should give you an idea of who is doing what out there.

Dan

P.S. An open source place and route tool exists, in addition to Arachne PNR which can be used for the iCE40 chips