FPGA(Opencl) code work well in emulator mode, but can't finish run on the FPGA

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But I considered that, in my code of last version, the printf information of kernel "weights_bias_in" can all printf out, so the kernel excute finished. That is to say, the other three kernels all start excute, read or write channels for many times before blocked. Especially for "conv", have been read “CONV1_WEIGHTS” for "num_feature_maps" times.

So, is not the problem of ordering of reading and writing of channels? Is the problem of FIFO(channel) confilict? Have you ever encounter the problem? Does Chaneel has the problem?I am not quite sure, so I also increaing the deapth of channel!

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Your observation is correct but there are a lot of unknown factors involved in the process. I recommend removing all the printf calls except the ones that are the beginning of your kernels.

If your host code is structured like this, it is correct (this is a pseudo code with shortened function names):

ClEnqueue(queue1, kernel1);

ClEnqueue(queue2, kernel2);

ClEnqueue(queue3, kernel3);

ClEnqueue(queue4, kernel4);

ClFinish(queue4);