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That one is different from what I mentioned above. The Terasic DE5-Net board does not have a power sensor, so I had to resort to estimating the power consumption based on the power consumption of the FPGA extracted from Quartus and the maximum power consumption of the memory module. What Quartus gives you is an estimation of the static power usage (close to idle configured power) and dynamic power usage with assumption of 12.5% toggling rate. I used static + dynamic + memory power consumption in this case as an estimation of total power consumption of the FPGA board, for meaningful comparison with the power consumption of CPU (chip only) and GPU (full board). Excluding the idle power (static power) of the FPGA board will not give you meaningful results because in many designs, the static power is actually higher than the dynamic power.
Right now I mostly rely on my Arria 10 board which includes a power sensor, and read the sensor in the same way as the sensor on the CPU or GPU boards since power measurement in this way will be much more accurate than estimating with Quartus. Some people also use an external power meter on the wall, and subtract the idle power of the system from the system power consumption during FPGA execution, to extract the total power consumption of the FPGA board, but this will never be as accurate as reading the power sensor on the FPGA board (if any).
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Got you thanks!!
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