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Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

foreach in systemverilog

What is wrong with this piece of code? Questa has no problem with it but Quartus does. Quartus has no issues with it if I remove the foreach and replace it with generate statement.

always_ff@(posedge register_if.clk or negedge register_if.rstn)

if(!register_if.rstn)

begin

foreach (int_stat_update_cnt_reg[intStatIter]) begin

int_stat_update_cnt_reg[intStatIter] <= 'd0;

end

foreach (int_stat_cnt_reg[intStatIter]) begin

int_stat_cnt_reg[intStatIter] <= 'd0;

end

end

<... snip ...>

Generate statement as below works -

genvar intStatIter;

generate for (intStatIter=0;intStatIter<NUM_OF_INT_STAT_REG; intStatIter+=1)

begin : intStat_gen

always_ff@(posedge register_if.clk or negedge register_if.rstn)

if(!register_if.rstn)

begin

//foreach (int_stat_update_cnt_reg[intStatIter]) begin

int_stat_update_cnt_reg[intStatIter] <= 'd0;

//end

//foreach (int_stat_cnt_reg[intStatIter]) begin

int_stat_cnt_reg[intStatIter] <= 'd0;

//end

end

2 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    13 years ago

    Yes! Of course... Quartus does not compile with foreach statement... I just assumed that it was obvious because all I use Quartus is to compile the code i.e. synthesize and p&r.

    Quartus thinks it's a syntax error atleast the error seems to suggest that. Don't remember or have the exact error in front of me. But it doesn't matter any more since Altera's support indicated that "foreach" statement is not supported Quartus 12.0. Quartus 12.0 help seems to indicate all loop constructs are supported.