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Altera_Forum
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17 years ago

Forcing FPGA signal using SignalTap Logic Analizer

Hi. I am looking some possibility to force Altera's internal signals (wires or registers) using Quartus tools. As I remember, in Xilinx development tool ISE I could assign values to internal sig...
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Altera_Forum
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17 years ago

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... use a Source & Probe instance...

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For the documentation, see the Quartus handbook, Volume 3, Section V, Chapter 17, "Design Debugging Using In-System Sources and Probes".

Depending on what you are trying to accomplish, the ECO design flow might work. It lets you make/change some routing connections, change LUT contents, etc. without running a full recompilation. That's covered in Volume 2, Section IV, Chapter 13, "Engineering Change Management with the Chip Planner".