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Altera_Forum
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17 years ago

Forcing FPGA signal using SignalTap Logic Analizer

Hi. I am looking some possibility to force Altera's internal signals (wires or registers) using Quartus tools. As I remember, in Xilinx development tool ISE I could assign values to internal sig...
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Altera_Forum
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17 years ago

The only option to force an internal signal is to use a Source & Probe instance and add a multiplexer to the design, that switches each individual signal to a source & probe output.