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chris_notsch's avatar
chris_notsch
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5 years ago

Forcibly specify correct toggle rate for LVDS pin

Dear Community, We are facing a critical issue in implementing a design using a Cyclone 10 LP with a pwm generator logic driving a LVDS pin. The resolution of the output logic is 1ns (1 Ghz delay...
JonWay_altera's avatar
JonWay_altera
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5 years ago

Hi Chris,

Could you attach a simplified design that shows the error?

chris_notsch's avatar
chris_notsch
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5 years ago

Yes, give me a few hours. I am working on a test program for this issue at the moment. I will attempt to modify it so it reflects the real application as close as possible.