Forcibly specify correct toggle rate for LVDS pin

Yes and no:

Implement reliably on a board: Yes, on the Intel EK-10CL025U256

1Gbps data rate: Yes & No: The edge position resolution is 1ns (thus information is transmitted technically with 1Gbps), however the pin can only toggle with at most 62.5MHz as it is impossible for the coounter to reset in less than 16 cycles with the output going high at least once per period.

It is possible to toggle the pin high or for a single cycle, which results in a well defined output signal with a clean signal, that is eighter high or low for only 1ns, but not both, the period is at least 16 cycles.

In essence, the transition edges are positioned using 1GHz clock, the square signal however toggles with max. 62.5Mhz. Should glitches occur when the on/off times are lower than 2ns, this is perfectly acceptable since all the driven external circuitry would recognize this as noise and ignore it entirely anyway.

Edit: During development i managed to test also toggle rates on TTL pins that were according to the design limits not capable of toggle rates of over 500MHz (and in case quartus detected it based on the logic used to drive the pin, rejected with a similar error; For that experiment i could afford extra locic, so i used secondary inputs that i then tied to VCC to trick quartus into thinking the pin would not toggle at that rate - this is no longer an option as the final implementation does not allow for any extra delays before the output.) at up to 1.3GHz and the output signal was still well enough defined for what we need. This may well be a reliability topic and may cause other potentially unexpected behaviour, however it it would be nice to at least be possible to bypass the error, as the device is clearly capable of operating in those conditions.