force_type confusion

Resolved refers to resolved types in VHDL or 4 state logic in Verilog.

In VHDL, resolved types are allowed multiple drivers. For example, if you have a signal declared as a std_logic, if you drive it with '1' and '0' from two difference sources, you get 'X'. (you'll get similar results for a reg or wire in verilog).

It is illegal to have two drivers on a signal of an unresolved type (like an integer in VHDL).

But the big question is why are you using the force command at all? Force is only really used to inject faults, and shouldnt be used to normally drive the design - this is what a testbench is for.