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Honored Contributor
Honored ContributorForce synthesis to fail if RAM cannot be inferred?
Hi, we have a design where there are a few large memories, declared as verilog reg[][]'s, which must be implemented as M9Ks. The design can't possibly fit the device or meet timing if they are imple...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- I'm glad at least one person here understood my question. --- Quote End --- Exactly. That is why I posted the dual-port implementation above that does NOT use any vendor proprietary functions. It is multi vendor.
