Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
9 years ago

Force synthesis to fail if RAM cannot be inferred?

Hi, we have a design where there are a few large memories, declared as verilog reg[][]'s, which must be implemented as M9Ks. The design can't possibly fit the device or meet timing if they are imple...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
9 years ago

--- Quote Start ---

Why don't use the MegaWizard? It is easy and confident. You can easily force Quartus to infer Block RAM for your memory. There is a check box when you generate the ip core which forces Quartus to use M9K (If your device has M9K, it may be M4K, etc).

--- Quote End ---

Because using the megawizard doesnt let you paramterise your block, or use your design in another vendor's tools.