Forum Discussion
Ryan-SEU
New Contributor
New ContributorFor the instantiation of ddr3, when compiling to the fitter step, an error error occurs: 14566.
In my PCB design, I usedcyclone V series FPGA and two pieces of Micron DDR3 SDRAM. I completed the parameter configuration of the IP core according to the guidelines , but when I was instantiating, w...
Hi Adzim,
Thank you for your reply!
I have solved this problem. The reason is that the PLL reference clock used for the first time cannot be routed to the bank where the DDR3 is located, so quartus prompts me with the above error message. When I changed another reference clock, the problem went away.
Ryan-SEU
AdzimZM_Altera
Regular Contributor
Regular ContributorI’m glad that your question has been addressed, I now transition this thread to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.
