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Ryan-SEU's avatar
Ryan-SEU
Icon for New Contributor rankNew Contributor
4 years ago
Solved

For the instantiation of ddr3, when compiling to the fitter step, an error error occurs: 14566.

In my PCB design, I usedcyclone V series FPGA and two pieces of Micron DDR3 SDRAM. I completed the parameter configuration of the IP core according to the guidelines , but when I was instantiating, w...
  • Ryan-SEU's avatar
    Ryan-SEU
    4 years ago

    Hi Adzim,

    Thank you for your reply!

    I have solved this problem. The reason is that the PLL reference clock used for the first time cannot be routed to the bank where the DDR3 is located, so quartus prompts me with the above error message. When I changed another reference clock, the problem went away.

    Ryan-SEU

sstrell's avatar
sstrell
Icon for Super Contributor rankSuper Contributor
4 years ago

As the error states, your placement selections are preventing the placement of a DLL for the memory interface.

When placing the pins in the Pin Planner, did you enable the DQ/DQS view to see the valid locations to place the DQ/DQS pins? Did you run the .tcl script that is created when you generate the IP (I think it's called pin_assignments.tcl)?

Ryan-SEU's avatar
Ryan-SEU
Icon for New Contributor rankNew Contributor
4 years ago

Hi sstrell,

Thank you for your reply!

I have solved this problem. The reason is that the PLL reference clock used for the first time cannot be routed to the bank where the DDR3 is located, so quartus prompts me with the above error message. When I changed another reference clock, the problem went away.

Ryan-SEU