For Loop Synthesis Problem

I don't know Verilog enough to know how the code should work. I know that in a VHDL process, if you use a variable it should work as expected.

When you talk about iterations you are thinking like a software designer instead of hardware. When you think about the hardware that is generated from your code, there isn't any iterations, everything is done in parallel. I guess that after optimization, both the algorithm with index+1 and index*2 would generate the same hardware.