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Altera_Forum's avatar
Altera_Forum
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8 years ago

"For... Loop" simulates differently then discrete assignments?

Can someone help me understand why the first code snippet works as I would expect it, but the second snippet simulation holds all values at 'U'? Note: WRITE_ENABLE_FIBRE_REG(0) is assigned in a di...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
8 years ago

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use std_ulogic and std_ulogic_vectors. They are unresolved types and never allow multiple drivers.

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If anyone is interested, Tricky is correct. When I changed the loop code to std_ulogic_vector I got the following:

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** Error: (vsim-3344) Signal "/receive_path_tb/DUT/WRITE_ENABLE_FIBRE_REG(0)" has multiple drivers but is not a resolved signal.

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Cheers Tricky!