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Altera_Forum's avatar
Altera_Forum
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8 years ago

"For... Loop" simulates differently then discrete assignments?

Can someone help me understand why the first code snippet works as I would expect it, but the second snippet simulation holds all values at 'U'? Note: WRITE_ENABLE_FIBRE_REG(0) is assigned in a di...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
8 years ago

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Thanks, that is interesting. I'm surprised I didn't see a 'multiple driver' warning or something similar. At least I'll know to avoid doing that going forward.

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You wont get a multiple driver warning in simulation because std_logic is a resolved type and allows multiple drivers. If it worked in synthesis, its probably because the Quartus compiler isnt very strict when it comes to some HDL rules.

If you wanted the multiple drivers to pop out in simulation, then use std_ulogic and std_ulogic_vectors. They are unresolved types and never allow multiple drivers.