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Honored Contributor
Honored Contributor"For... Loop" simulates differently then discrete assignments?
Can someone help me understand why the first code snippet works as I would expect it, but the second snippet simulation holds all values at 'U'? Note: WRITE_ENABLE_FIBRE_REG(0) is assigned in a di...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- I can assure you that, other then WRITE_ENABLE_FIBRE_REG(0), there are no assignments outside this process. --- Quote End --- This will be the reason why it wasnt working. When you use a loop, the compiler does not know which bits are set and which are not, so when you assign even 1 bit inside the loop, it assumes all the bits are driven in the process. This leads to a multiple driver error on any bits assigned outside the process. This is just how VHDL works and NOT and error with the compiler. moral of the story - if you use a loop, you MUST assign ALL bits for that signal inside the process. This is why your temporary version works, as you do assign WRITE_ENABLE_FIBRE_REG_TEST inside the loop.
