For loop, array and a step motor, VHDL

look I developed this code for a stepper motor with a sequence and I hope you serve :)

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_arith.all;

entity mtrpas is

port(

clock,reset:in std_logic;

clkout:inout std_logic;

push_l ,push_r: in std_logic;

pasos2: out std_logic_vector(3 downto 0);

pasos: out std_logic_vector(3 downto 0));

end mtrpas;

architecture archi_mtrpas of mtrpas is

CONSTANT max: INTEGER := 50000000;

CONSTANT half: INTEGER := max/10;

SIGNAL count: INTEGER RANGE 0 TO half;

begin

PROCESS

BEGIN

WAIT UNTIL clock'EVENT and clock= '1';

IF (count < max) THEN

count <= count + 1;

ELSE

count <= 0;

END IF;

IF (count < half)THEN

clkout <= '0';

ELSE

clkout <= '1';

END IF;

END PROCESS;

--------------------------------------------

process(push_l ,push_r,reset,clkout)

variable cuenta: integer range 0 to 5:=0;

begin

if clkout'event and clkout='1' then

if(reset='0') then

cuenta:=0;

else

if(push_l='1') then

cuenta:=cuenta+1;

if(cuenta=5) then

cuenta:=0;

end if;

end if;

if(push_r='1') then

cuenta:=cuenta-1;

if(cuenta=0) then

cuenta:=4;

end if;

end if;

end if;

end if;

case cuenta is

when 0=> pasos<="0000";pasos2<="0000";

when 1=> pasos<="1000";pasos2<="1000";

when 2=> pasos<="0100";pasos2<="0100";

when 3=> pasos<="0010";pasos2<="0010";

when 4=> pasos<="0001";pasos2<="0001";

when others => null;

end case;

end process;

end archi_mtrpas;