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The for loop statement in vhdl it's different from the for sentence of C. For loop is not a sequential statement. It is used when you need to copy paste many times a circuit cell ( iterative circuit ).
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Sorry to be a pedant, but a for loop IS a sequential statement. It will work exactly like it's C counterpart in the right situations - but only in simulation. The Synthesisor will unroll the loop and create parrallel logic as you describe, but the behaviour of a for loop can be important in testbenches. If you want "sequential" code inside a for loop, you can use a variable instead of a signal updating between iterations (but then you'll get a long chain of logic).
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