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Altera_Forum
Honored Contributor
12 years agoLooking the code it seems you are a C programmer. The for loop statement in vhdl it's different from the for sentence of C. For loop is not a sequential statement. It is used when you need to copy paste many times a circuit cell ( iterative circuit ).
Probably you're tried to explore the 8 output value you write in secuencia. A counter may solve it: architecture Behavioral of main is signal sec_reg, sec_next : unsigned(2 downto 0); secuencia := ("0000", "0001", "0010", "0011", "0100", "0101", "0110", "0111"); begin process( clr_n, clk ) begin if( clr_n = '0' ) then sec_reg <= ( others => '0' ); sal_reg <= "0000"; elsif( clk'event and clk = '1 ) then sec_reg <= sec_next; sal_next <= sal_next; end if; end process; sec_next <= sec_reg + 1; motor <= sal_reg; process(sec_reg) begin case sec_reg is when "0000" => sal_next <= "0000"; when "0001" => sal_next <= "0001"; -- complete the rest end case; end process; end Behavioral; There something missing in this code. To drive a stepper motor you need to slow down the clock.