Hello, In the Time Quest, the Fmax for my design is 303 MHz , but the Restricted Fmax is 250 MHz with a Note that says 'limit due to minimum period restriction (max I/O toggle rate)' . The clock frequency = 333 MHz. Does this mean that I need to operate the design not beyond 250 MHz or will 303 MHz work too? Thanks

--- Quote Start --- Hello, In the Time Quest, the Fmax for my design is 303 MHz , but the Restricted Fmax is 250 MHz with a Note that says 'limit due to minimum period restriction (max I/O toggle rate)' . The clock frequency = 333 MHz. Does this mean that I need to operate the design not beyond 250 MHz or will 303 MHz work too? Thanks --- Quote End --- I am afraid yes the ultimate fmax is that figure of the most restrictive case.

The restricted fmax is usually due to the part you are using.

--- Quote Start --- The restricted fmax is usually due to the part you are using. --- Quote End --- Tricky.. I did not understand your reply. Can you please explain what it means?

There are different speed grades of chip, Like C1,2,3,4 etc. These will have restricted FMax because they are not as strict on testing the dies as the number increases. So C1 will have a higher restricted FMax than a C5

I have a few more questions. 1) What exactly is the difference between a netlist and a timing netlist? 2) How is the Fmax and Restricted Fmax calculated? One of the report says: "Restricted fmax considers hold timing in addition to setup timing, as well as minimum pulse and minimum period restrictions. " But nothing is said about the unrestricted Fmax. Does it mean that unrestricted Fmax considers only setup time? 3) Now the restriction is only due to the width of the clock cycle and not due to the "delay" of the circuit. Will it make sense to consider Fmax and NOT restricted Fmax if we take only propagation delay into consideration? Thank you.

Fmax and Restricted Max | Altera Community

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Altera_Forum
Honored Contributor
12 years ago
wow, thanks for the tip
Altera_Forum
Honored Contributor
12 years ago
--- Quote Start ---
wow, thanks for the tip
--- Quote End ---

I tried to visualise the case given by Altera and I believe it is not straight forward. It seems the only case for hold check to limit fmax. I believe they mean the case when launch and latch registers are both sampling on same edge (rising edge,or falling edge) but the clock is inverted. This means there would be some half period delay of the latch clock relative to launch clock and the tool will need to be given instruction not to check current launch with next latch(for setup) as it is too restrictive, instead a multicycle of 2 is to be applied by user for tool's sake(this is not a true two clock multicycle). Thus the data launched may hit latch hold window or latch setup window and as such either may restrict fmax.

I am still puzzled why the tool does not give any red warnings on hold slack in our case, neither it tells where the problem lives.

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Fmax and Restricted Max

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