fixing inferred latch

If the above code is exactly what you compiled, you get the warning for a for loop index variable. It would never create a register or latch by Verilog specification. It's different from the possible false warnings addressed by the above quoted Quartus help file.

My experience with Quartus VHDL compiler says, that "inferred latch" warnings are mostly correct, indicating intended or unintended asynchronous latches. I'm only occasionally coding Verilog, but I didn't yet notice extensive false warnings.