Forum Discussion
New ContributorFitter errors trying to convert old qpf to newer quartus/device
Hi Ryan
Sorry for late response.
Can you try to remove those board trace model assignment with OUTPUT_IO_TIMING_NEAR_END_VMEAS and OUTPUT_IO_TIMING_FAR_END_VMEAS? Those assignment might not supported by certain devices.
Cross family device migration has no direct flow. We have to review from various aspect such as pin assignment, IP migration, parameter setting and etc. The suggested migration is vertical migration within the same family which can be referred to datasheet of each family.
Thanks.
Eng Wei
New ContributorThanks for the response!
Commenting out those lines in the .qsf did allow compilation to finish.
However, I was hoping to get an estimation of Fmax in the timing reports, but they state there are "no paths to report." The clock status summary shows an unconstrained clock called clock_50. There are a few warnings associated with clock_50 in the Timing Analyzer messages, including message IDs 332174, 332049 and 332060. The gist of these messages is essentially: "clock_50 could not be matched with a port", "ignored create_clock" and "clock_50 was determined to be a clock but was found without and associated clock assignment", respectively.
Do you have any suggestions for "constraining" this clock and producing an Fmax estimation?
Super ContributorYou have to create a .sdc file that defines, at a minimum, the clocks and external I/O timing of the design. To learn about timing analysis and the timing analyzer, start here:
https://www.intel.com/content/www/us/en/programmable/support/training/course/odsw1115.html
