First VHDL try

BEGIN

dec:PROCESS(a(15 downto 0))

BEGIN

--1

if( a(15 downto 6) = "0100000110" and a(4 downto 0) = "00100" )

then dq(8 downto 1) <= "10111111";

--2

elsif( a(15 downto 14) = "01" and a(5 downto 4) = "00")

then dq(8 downto 1) <= "01111111";

--3

elsif( a(15 downto 8) = "01111111" and a(5 downto 4) = "10")

then dq(8 downto 1) <= "01111111";

--4

elsif( a(15 downto 13) = "010" and a(5 downto 4) = "10")

then dq(8 downto 1) <= "01111111";

--5

elsif( a(15 downto 12) = "0110" and a(5 downto 4) = "10")

then dq(8 downto 1) <= "01111111";

--6

elsif( a(15 downto 11) = "01110" and a(5 downto 4) = "10")

then dq(8 downto 1) <= "01111111";

--7

elsif( a(15 downto 10) = "011110" and a(5 downto 4) = "10")

then dq(8 downto 1) <= "01111111";

end if;

END PROCESS dec;

END bus_decode;