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Altera_Forum's avatar
Altera_Forum
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9 years ago

Filter VHDL

Hi, I've designed a filter pass low with 64 taps. I am not sur about my coding and I will be grateful if someone correct or confirm my vhd file. I have some doubts about the output signal. An...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
9 years ago

Hi,

I had a quick review of your code. First answer few questions:

1. Where are your filter coeficients? Are you trying implement moving average filter?

2. What type of filter you are trying to implement? FIR (Finite Impulse Response ) or IIR (Infinite inpulse response)?

Some comments on your code:

Your code sums up input signal 64 times with itself. For eg. if signal_in=1 then you will get DOUT(63)=64. This is not how digital filters works.