Filter VHDL

Hi,

my first thoughts:

• yep, should have low-pass behavior

• FIR design, so it'll be stable

• your code could need some indentation, and is written in a bit complicated way, but that's fine

• your simulation is not labeled, I can just do educated guesses on what's going on

Then I tried to simulate it and realized that it didn't work, as you didn't put any "library" or "use" clause into it. And there's no test bench. If you want help from people, meet them half-way ;-)

Then you did not specify what your goal was. It looks like a simple FIR-filter with all gains set to one. Did you choose that deliberately? Because it looks like you were just experimenting.

I don't know how much knowledge you have about filters, so here are a few hints to get started:

• Wikipedia basics about FIR an IIR: https://en.wikipedia.org/wiki/infinite_impulse_response (https://en.wikipedia.org/wiki/infinite_impulse_response), https://en.wikipedia.org/wiki/finite_impulse_response (https://en.wikipedia.org/wiki/finite_impulse_response)

• Use Scilab to calculate filter coefficients for real filters: https://help.scilab.org/docs/6.0.0/en_us/eqiir.html (https://help.scilab.org/docs/6.0.0/en_us/eqiir.html)

• Use fixed-point arithmetic in VHDL to easily model those filters: https://web.archive.org/web/20160313200350/http://vhdl.org/fphdl/index.html (https://web.archive.org/web/20160313200350/http://vhdl.org/fphdl/index.html)

Does any of that help maybe?

Best regards,

GooGooCluster

Hi,

I had a quick review of your code. First answer few questions:

1. Where are your filter coeficients? Are you trying implement moving average filter?

2. What type of filter you are trying to implement? FIR (Finite Impulse Response ) or IIR (Infinite inpulse response)?

Some comments on your code:

Your code sums up input signal 64 times with itself. For eg. if signal_in=1 then you will get DOUT(63)=64. This is not how digital filters works.