FIFO synthesized away but simulates fine

Synthesis removes all design parts that are useless in hardware terms because they don't contribute to existing output signals. In functional simulation, you can still watch their internal states.

The reason, why a design entity is functionless may not be obvious at first sight. It can be e.g. an unconnected clock or reset signal, or a missing transition in a state machine. If you read the synthesis report thoroughly, you should be able to detect where the removal takes a start.