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Altera_Forum's avatar
Altera_Forum
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14 years ago

FIFO synthesized away but simulates fine

I'm having a problem where I have instantiated a FIFO in my design. When I compile the design it tells me the RAM module inside the FIFO has been synthesized away but when I take the exact same desig...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

I can definately tell it has synthesized away most of my design, I just don't know why. What is the likely reason it would do this and why does simulation work?