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Altera_Forum's avatar
Altera_Forum
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14 years ago

FIFO synthesized away but simulates fine

I'm having a problem where I have instantiated a FIFO in my design. When I compile the design it tells me the RAM module inside the FIFO has been synthesized away but when I take the exact same desig...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

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Or is it possibly another problem I cannot figure out?

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Its another problem you have not yet figured out.

Get Quartus to generate a .vo or .vho output file for the synthesized design, and then simulate that in Modelsim.

If you have a decent testbench, you should be able to determine the difference between your original HDL file, and the synthesized logic.

Alternatively, (or in addition) use SignalTap within the hardware to check that each interface is working correctly.

Cheers,

Dave