Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

FIFO queue

hey everyone, I was wondering how to write a FIFO queue code using verilog. I am unable to start it even. it will be great if someone can help me in this matter. Cheers Muzammil
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

The dispatcher IP core in this design has a on-chip memory based FIFO in it that you could look at: http://www.alterawiki.com/wiki/modular_sgdma

Typically you just instantiate the scfifo or dcfifo megacores in your design if you need a FIFO. That design above only creates a FIFO because it needed to have byte enables to qualify the data going into the FIFO.