Honored Contributora group of bidir pins were assigned to fast input register/fast output register/fast output enable register by assignment editor.
the fit result shows that they ware assigned to fast input register only without warning. the output delay of those pins are longer than clock period, i have to use fast output register to reduce the output delay.
Honored ContributorYou must make sure there is no combinatorial function in the output register path, e.g.
Process( clk )
begin
if rising_edge( clk ) then
lq <= function( ...) ;
end if ;
end process ;
Q <= lq when (qvalid = '1') else (others => '0') ;
dose it means that the output signal processing should be divided into two part,
one is combinational logic, the other is sequential logic? in this case, it would be necessary to get output signal through combinational logic, the sequential should be as simple as possible. i suppose the reason is fast output register did not have enable pin. but what fast output enable register mean?
