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Altera_Forum
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12 years ago

False latching error

Hi, When I synthesize my design in QUARTUS II I get the error: Error (10166): SystemVerilog RTL Coding error at hmon_eeprom.sv(59): always_comb construct does not infer purely combinational logi...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

The code needs to infer latches for bus2ip_data which isn't assigned in all case items.

You can enforce pure combinational logic by assigning the default values unconditionally in front of the case statement.

I don't see a purpose of using casez.