Failure for initialization ROM memory by using $readmemh task

Hi,

The mips_mem is the part of the MIPS processor design. The testbench was used to test hold processor,

// Top module for the MIPS processor core
// NOT synthesizable Verilog!
`timescale 1ns/100ps

module testbench;

   reg [31:0] i;
   reg [29:0] addr;
   reg 	       rst_b;
   wire halted;
   
   //parameter
   parameter start = 0, halfPeriod = 50;
   reg 	     clk;
   // The clock
   initial
     clk = start;
   
   always
     #halfPeriod clk = ~clk;

   // The mips_top core
   mips_top inst_mips(.clk(clk), .rst_b(rst_b), .halted(halted));

   initial
     begin
	rst_b = 0;
	#75;
	rst_b <= 1;
     end

   always @(halted)
     begin
	#0;
	if(halted === 1'b1)
	  $finish;
     end
   

endmodule

Hi, I attached the design .qar file to this post.