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chunxi_yu's avatar
chunxi_yu
Icon for New Contributor rankNew Contributor
2 years ago
Solved

Failed to create SystemVerilog interface in _hw.tcl in Platform Designer

Hi, I am using Cyclone V and Quartus Prime Standard 22.1.2 (which is the latest downloadable version in Intel website). There is a user component with 2 AXI interfaces and 1 APB interface in Platfo...
ShengN_altera's avatar
ShengN_altera
Icon for Super Contributor rankSuper Contributor
2 years ago

Hi Chunxi ,

In component editor, add the <systemverilog_interface>.sv and <systemverilog_top_module>.sv. Then, set attribute of <systemverilog_top_module>.sv to Top-level File and click Analyze Synthesis File will do. Systemverilog interface module will be linked to systemverilog top module automatically. Attached file for your reference.

Thanks,

Best Regards,

Sheng

chunxi_yu's avatar
chunxi_yu
Icon for New Contributor rankNew Contributor
2 years ago

Hi Sheng,

I see your attachement. It is an example of SV interface used inside the RTL but not as a top-level port.

Instead of this:

module or_ex( //top-level
input logic[3:0] a, b,
output logic[5:0] sum, sum_new,
input logic clock_sink_clk, reset_sink_reset
);
logic_gate_if lg (); // import all signals from interface

Is it possible for Platform Designer to extract signals and corresponds them to IP component interface from below code?

module or_ex( //top-level
logic_gate_if.sink lg;
output logic[5:0] sum, sum_new,
input logic clock_sink_clk, reset_sink_reset
);

Or is the "add sv interface" command in Prime pro edition unable to do this either?

Thanks,

Chunxi