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Altera_Forum
Honored Contributor
10 years agoExpression has 8 elements, but must have 9 elements, and also, else null
Hi, I have this variable, X, which is an std_logic_vector(8 downto 0). I have inputs A,B,C which are std_logic_vector(7 downto 0). Also, a signal D which is also std_logic_vector(7 downto 0)....
Altera_Forum
Honored Contributor
10 years agoThanks (again) for your comprehensive answer, Tricky. I did used the unsigned library, and I will try what you suggested.
As for the second question... do you have a recommendation on a good book/website on proper writing of VHDL code? I want to be able to write efficiently and understand the logic, like you said. A lot of times I run into logical errors and would love to really understand them and understand what I'm doing, because currently it seems like I'm just writing a piece of code and hoping to get it right.