Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

Exporting PLL outputs through conduits in Qsys

Hi all, I am working on a FPGA design using Qsys software, however, I have some problems connecting signals among components. In the figure that I have uploaded you can see a part of th...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

You said: "The customized subsystem has two clock inputs, and two conduit inputs (red lines). " shouldn't this be " ...and two conduit outputs (red lines). ". These outputs connect to pins in your FPGA which you connect to your external subsystem inputs. Why can't they drive your external subsystem? Do you have a square wave (clock signal) on these pins before you connect them to the inputs of your external subsystem?