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Honored Contributor
Honored ContributorExporting PLL outputs through conduits in Qsys
Hi all, I am working on a FPGA design using Qsys software, however, I have some problems connecting signals among components. In the figure that I have uploaded you can see a part of th...
Altera_ForumHonored Contributor
Honored ContributorYou said: "The customized subsystem has two clock inputs, and two conduit inputs (red lines). " shouldn't this be " ...and two conduit outputs (red lines). ". These outputs connect to pins in your FPGA which you connect to your external subsystem inputs. Why can't they drive your external subsystem? Do you have a square wave (clock signal) on these pins before you connect them to the inputs of your external subsystem?
